sp8402 very low phase noise divider by 2 n september 2005 the sp8402 is a very low phase noise divider which divides by powers of two. the s0, s1, s2 data inputs select the division ratio in the range 2 1 to 2 8 . special circuits techniques have been used to reduce the phase noise considerably below that produced by standard dividers. the data inputs are cmos or ttl compatible. the sp8402 is packaged in a 28 pin plastic so package to be compatible with the sp8400 and sp8401 devices. features very low phase noise (typically -155 to 160dbc/hz at 1khz offset) supply voltage 5v absolute maximum ratings supply voltage 6.5v output current 20ma storage temperature range -55 c to +125 c maximum clock input voltage 2.5v p-p mp28 fig.1 pin connections - top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 n/c n/c n/c v cc +5v gnd clock input clock input clock input gnd v cc +5v v cc +5v n/c s0 n/c n/c n/c n/c n/c n/c n/c output output n/c v cc +5v n/c s2 s1 clock input fig.2 typical single sideband phase noise measured at 768mhz (f) (dbc/hz) ?db frequency (hz) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 ?40 ?50 ?60 ?70 10 100 1k 10k 100k ordering information sp8402/kg/mpes 28 pin soic tubes sp8402/kg/mpfp 28 pin soic* tubes sp8402/kg/mp1t 28 pin soic tape & reel *pb free matte tin 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copy right 1994-2005, zarlink semiconductor inc. all rights reserved.
2 sp8402 fig.3 typical input sensitivity electrical characteristics guaranteed over: supply voltage v cc = +4.75v to +5.25v temperature t amb = -10 c to +75 c tested at +4.75v and +5.25v at t amb = +25 c frequency mhz 400 300 200 100 0 200 400 600 800 1000 1200 1400 355mv 140mv operating window 1600 500 600 v in mv rms min. typ. max. supply current output voltage swing input sensitivity 200mhz to 1.5ghz data inputs logic high voltage low low voltage input current 92 410 102 140 (-4) 0.8 180 82 320 2.2 4, 11, 12, 18 20, 21 7, 8 output loaded with 300r see fig.5 p-p @ 1.4ghz input 256 mode outputs loaded with 330r see fig.5 rms sine wave into 50 ohms (dbm equivalent) see fig.3 5v data input voltage ma mv mv dbm v v a units value conditions characteristic pin s0 l h l h l h l h s1 l l h h l l h h s2 l l l l h h h h division ratio 2 4 8 16 32 64 128 256 fig.4 truth table
3 sp8402 fig.5 test circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 sp8402 10nf 10nf 1nf 1nf 2x330r 1nf ttl/cmos modulus control 220nf 50r output v cc rf 50r signal generator
4 sp8402 fig.5 typical application combining output to increase signal and retain low phase noise 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 sp8402 10nf 10nf 1nf 1nf 2x330r 1nf s0 s1 s2 50r 10nf output 10 f +5v clock input
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